1. Technical Field
The present disclosure relates to a method for biasing an EEPROM (Electrically Erasable and Programmable Read-Only Memory) non-volatile memory array, in its various operating conditions, and to a corresponding EEPROM non-volatile memory device.
2. Description of the Related Art
As is known, an EEPROM array is constituted by a plurality of memory cells, arranged aligned in rows and columns and connected to appropriate selection and biasing elements and stages, which enable programming (or writing), erasing, and reading thereof in respective operating conditions. Each memory cell is formed by a floating-gate transistor, and the operations of erasing and programming envisage the injection and, respectively, the extraction of electrical charges into/from the floating-gate terminal of the floating-gate transistor via the tunnel effect (Fowler-Nordheim effect). Programmed memory cells have a different threshold voltage from erased memory cells; the reading operation of the contents of the memory cells hence envisages application of an appropriate read biasing voltage to the floating-gate terminal of the respective floating-gate transistors (which has a value intermediate between the threshold-voltage values of programmed and erased memory cells), and determination, on the basis of the presence or absence of conduction of electrical current through the floating-gate transistors, of the state (programmed or erased) of the memory cells.
As illustrated schematically in FIG. 1, a typical EEPROM array, designated as a whole by 1, is constituted by a certain number Nwl of rows and Nwl wordlines 1a, each row provided with a wordline WL, i.e., a line of conductive material, typically metal, which extends horizontally along the entire row. Each row, e.g., the row 1b provided with WORDLINE [0] 1c, is made up of a certain number Nwords of words 1d, and each word is in turn made up of a certain number Nbits of memory cells 1e, each storing a respective bit according to the state (programmed or erased). Each row is moreover traversed by a certain number of source lines SL, which extend vertically along the entire extension of the columns of the array at given intervals, for example every two words, and by a plurality of gate-control lines Cgt, one for each word.
In greater detail, FIG. 2 shows the architecture of a portion of the EEPROM array 1, including two wordlines WL[n], WL[n+1], each of which comprising two words and two associated gate-control lines Cgt[i], Cgt[i+1].
The memory cells, designated by 2, which are aligned vertically along one and the same column, have drain terminals selectively connected to one and the same bitline BL, constituted by a metal line extending vertically parallel to the gate-control lines Cgt, through a respective selection transistor 3, of an NMOS type. The selection transistors 3 of one and the same row have gate terminals connected to one another by the respective wordline WL. Each selection transistor 3 moreover has its drain terminal connected to a respective bitline BL and its source terminal connected to the drain terminal of an associated memory cell 2.
The gate terminals of the memory cells 2 belonging to one and the same word are connected to one another via a horizontal connection line, selectively connected to a respective gate-control line Cgt via a byte switch 4, which is also constituted by a transistor of an NMOS type. Each byte switch 4 has its source terminal connected to the gate terminals of the memory cells 2 of the corresponding word, its drain terminal connected to the respective gate-control line Cgt, and its gate terminal connected to the wordline WL of the respective row. Consequently, in this architecture, the wordlines WL enable supply of the appropriate biasing voltages simultaneously to the gate terminals of all the byte switches 4 and of all the selection transistors 3 belonging to one and the same row of the memory array 1. Furthermore, byte switches 4 belonging to one and the same column have drain terminals connected to the same gate-control line Cgt.
Memory cells 2 that are aligned horizontally along one and the same row moreover have source terminals connected to one another, generally constituted by a single doped region diffused within a substrate of semiconductor material, in which the memory array 1 is provided, or else by individual diffusions (one for each memory cell) connected to one another by a line of conductive material, typically metal; vertical source lines (SL) contact these source diffusions, traversing them in a vertical direction, at predetermined intervals, for example every two words of the memory array 1.
In a way not illustrated herein, the EEPROM device, of which the memory array 1 forms part, comprises suitable biasing stages, which enable biasing with voltages of appropriate value (depending upon the operating conditions) of the various wordlines, bitlines, source lines, and gate-control lines of the memory array 1.
In particular, in use, the byte switches 4, appropriately biased by the respective wordlines WL, enable transfer of the biasing applied to the vertical gate-control lines Cgt to the gate terminals of the memory cells 2 of the respective word. The selection transistors 3, which are also appropriately biased by the respective wordline WL, enable transfer of the voltage applied to the vertical bitlines BL to the drain terminals of the respective memory cells 2.
In greater detail, during an erasing operation, the minimum erasable unit is constituted by a word of the memory array 1. With reference to FIG. 3, there is assumed, for example, erasing of the word biased by the wordline WL[n] and by the gate-control line Cgt[i].
To erase the memory cells 2 forming this word, an erasing voltage Verase is applied, typically of 13 V (in the case of 0.18 μm CMOS technology), between the gate and source terminals (VGs=Verase), and between the gate and drain terminals (VGD=Verase) of the memory cells 2. Typically, and as illustrated in FIG. 3, the gate voltage is forced equal to the value of the erasing voltage (VG=Verase), whilst the source voltage is set to the ground voltage (VS=0 V) so as to obtain the desired positive voltage VGS. On account of this value of the voltage between gate and source, the channel of the floating-gate transistors of the memory cells 2 is formed, and, since no drain current is flowing, the drain voltage is equal to the source voltage so that VGS=VGD=Verase, as desired.
Typically, to obtain erasing, the wordline WL[n] of the row to which the word to be erased belongs is biased at a first high voltage HVp1, generated via a charge-pump circuit starting from an internal supply voltage of the memory device, having for example a value of 16 V (in general, meant by “high voltage” is a voltage that is higher than, and not comparable with, low or logic voltage values, and typically has values higher than 10 V). Furthermore, the gate-control line Cgt[i] to which the word is associated is set to the erasing voltage Verase, whilst the source line SL is set to ground (0 V). The bitlines BL are instead left floating (or at a high impedance). The wordlines WL, as likewise the gate-control lines Cgt, not selected for the erasing operation, are set to ground.
In these biasing conditions, the byte switch 4 thus transfers to the gate terminals of the memory cells 2 of the word to be erased the erasing voltage Verase present on the gate-control line Cgt[i] (thanks to the presence of the first high voltage HVp1 on the corresponding control terminal, of a value sufficiently higher than the same erasing voltage Verase).
During a programming operation, the minimum programmable unit is instead constituted by the individual bit so that it is possible to program in the desired state each individual memory cell 2. With reference to FIG. 4, it is assumed for example to program the word biased by the wordline WL[n], by the gate-control line Cgt[i], and by the bitline BL[0].
To program this memory cell 2 a programming voltage Vprog is applied, typically equal to 13 V (once again in the case of CMOS technology at 0.18 μm), between the drain and gate terminals (VDG=Vprog), leaving the source terminal floating. In the practical common implementation, the biasing voltage Vprog is forced on the drain terminal (VD=Vprog), whilst the gate terminal is brought to ground (VG=0 V). For this purpose, the wordline WL[n], to which the memory cell 2 is coupled, is biased at the first high voltage HVp1, for example once again equal to 16 V; the corresponding gate-control line Cgt[i] is set to ground (0 V); the bitline BL[0] associated to the memory cell 2 is set to the programming voltage Vprog; and the source line SL is left floating. In this biasing condition, the gate terminal of the memory cell 2 to be programmed is brought to the voltage present on the gate-control line Cgt[i], via the byte switch 4 (which is set in a conduction condition by the first high voltage HVp1 present on the corresponding control terminal), and the programming voltage Vprog on the bitline BL[0] is transferred onto the drain terminal of the same memory cell 2, via the corresponding selection transistor 3, which is also set in a conduction condition by the biasing voltage of the associated wordline WL[n]. Once again, both the wordlines WL and the gate-control lines Cgt of the memory cells 2 not selected are set to ground, whilst the corresponding bitlines BL are left floating.
The memory cells 2 of the memory array 1 are in this way subjected to several work cycles, which cause, with the passage of time, an intrinsic reduction of the efficiency of the erasing and programming operations. In particular, phenomena of charge trapping and of natural ageing of the floating-gate transistors of the memory cells 2 cause a modification in time of the values of the threshold voltages of the erased and programmed memory cells.
In detail, as illustrated in FIG. 5 by a solid line, the threshold voltage Vt—e of the erased memory cells decreases, whilst the threshold voltage Vt—p of the programmed memory cells has a corresponding growth, as the work cycles increase. A reduction of the opening of the programming/erasing “window” consequently occurs in time, caused by the approach of the values of the different threshold voltages of the programmed and erased memory cells, with the consequent possibility of reading errors and malfunctioning of the memory.
In particular, to aggravate this natural phenomenon of ageing of the memory cells 2, the biasing architecture previously described, typically used in prior art EEPROMs, leads to further stresses in the selection transistors 3 and in the byte switches 4, which cause electrical stresses at the gate terminals and an increase of the charge trapping in the oxides.
Basically, as illustrated in FIG. 5 by a dashed line, this biasing architecture leads to a further reduction of the programming/erasing window, which thus further adds to the intrinsic reduction presented by the memory cells subjected to several work cycles.
U.S. Pat. No. 6,934,192 describes a different architecture of an EEPROM array, which differs from the one previously illustrated on account of the presence of two distinct wordlines for each row of the memory array.
In particular, as illustrated in FIG. 6, in the memory array, designated here by 10, associated to each row is a first wordline, designated by WL_seltr, connected to which are the gate terminals of the selection transistors 3, and a second wordline, designated by WL_bsw, distinct and separate from the first wordline WL_seltr, connected to which are the gate terminals of the byte switches 4. The use of two wordlines for each row is described in the aforesaid document for the purposes of protection of the memory array 10 from the effects of a possible breakdown of the selection transistors 3 during the erasing operations, due to the possible failure of the gate oxides, in particular in such a way as to confine the effects of this breakdown to the individual memory cell subjected to failure, without involving other adjacent memory cells.
The two wordlines are biased at the same voltage during the reading and programming operations, whilst they are instead biased at different voltages during erasing, during which the first wordline WL_seltr is brought to the same voltage as the source terminal of the selection transistor 3 (i.e., to ground), whilst the second wordline WL_bsw is brought to the first high voltage HVp1. In this way, a possible breakdown of the selection transistor 3 (with a consequent short-circuit between the corresponding gate and source terminals) does not cause collapse towards ground of the output of the charge-pump circuit (which continues to supply at output the first high voltage HVp1) and the consequent impossibility of continuing the erasing procedure of the other memory cells 2 of the same word; in fact, a localized error occurs in the memory cell 2 that has undergone the breakdown phenomenon.
The known architecture of the memory array described above consequently aims at confining the effects of a breakdown (already occurred) in a single memory cell 2 or at the most in a limited number of them, but does not enable reduction beforehand of the possibility of said breakdown occurring. In particular, no solutions are described that are useful for reducing the electrical stresses acting on the transistors of the memory array 10 and hence preventing breakdown phenomena.